Suppression of image frequency mode in microprocessor-controlled frequency synthesising systems
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A simple method of starting a new acquisition cycle in microprocessor-controlled frequency synthesising systems in order to suppress the image frequency mode is described. The image frequency detector built into the 305-415 kHz first local oscillator - frequency synthesiser of a 20 Hz - 110 kHz selective voltmeter, supported by an Intel 80C39 microcontroller, identifies the appearance of the image frequency mode in the system and generates a signal to start the procedure carried out by the microcontroller. The microcontroller changes the reference frequency to suppress the signal at the variable input of the phase detector of the phase locked loop (PLL) containing a frequency mixer. This, in turn, forces the phase detector of this PLL to generate an increased voltage, up to 12V, across the associated varactor diode and, by increasing the loop frequency, restore proper functioning of the synthesiser.